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Classes |
| class | IpfTemplInfo |
| struct | IpfTemplInfo.TemplDesc |
| class | Encoder_32 |
| class | Encoder_128 |
| class | Register_Encoder_offset6 |
| class | Immediate_Encoder_offset6 |
| class | Opcode_Encoder_offset9 |
| class | Merced_Encoder |
| class | Merced_Encoder_File_Binary |
| struct | Template_Descr |
Defines |
| #define | IPF_INSTRUCTION_LEN 16 |
| #define | ENC_N_TMPLT 16 |
| #define | ENC_N_SLOTS 3 |
| #define | ENC_ALL_AVLB_TMPLTS 0x5bf7 |
Enumerations |
| enum | EM_Templates {
TMPLT_mii = 0,
TMPLT_miSi = 1,
TMPLT_mli = 2,
TMPLT_bad1 = 3,
TMPLT_mmi = 4,
TMPLT_mSmi = 5,
TMPLT_mfi = 6,
TMPLT_mmf = 7,
TMPLT_mib = 8,
TMPLT_mbb = 9,
TMPLT_bad2 = 10,
TMPLT_bbb = 11,
TMPLT_mmb = 12,
TMPLT_bad3 = 13,
TMPLT_mfb = 14,
TMPLT_bad4 = 15
} |
| enum | IpfSlotPos { IpfSlot0 = 0,
IpfSlot1 = 1,
IpfSlot2 = 2,
IpfNoSlot = 3
} |
| enum | IpfInstType {
IpfNull_Inst = 0,
IpfNop_Inst = 1,
IpfA_Inst = 2,
IpfM_Inst = 3,
IpfI_Inst = 4,
IpfF_Inst = 5,
IpfB_Inst = 6,
IpfX_Inst = 7
} |
| enum | EM_Syllable_Type {
ST_null = 0,
ST_n = 1,
ST_a = 2,
ST_m = 3,
ST_i = 4,
ST_f = 5,
ST_b = 6,
ST_il = 7,
ST_bl = 8,
ST_bn = 9,
ST_ma = 10,
ST_br = 11,
ST_fc = 12,
ST_is = 13,
ST_m0 = 14,
ST_last_type = 14,
ST_first_real = ST_a
} |
| enum | EM_Application_Register {
AR_kr0 = 0,
AR_kr1 = 1,
AR_kr2 = 2,
AR_kr3 = 3,
AR_kr4 = 4,
AR_kr5 = 5,
AR_kr6 = 6,
AR_kr7 = 7,
AR_rsc = 16,
AR_bsp = 17,
AR_bspstore = 18,
AR_rnat = 19,
AR_fcr = 21,
AR_eflag = 24,
AR_csd = 25,
AR_ssd = 26,
AR_cflg = 27,
AR_fsr = 28,
AR_fir = 29,
AR_fdr = 30,
AR_ccv = 32,
AR_unat = 36,
AR_fpsr = 40,
AR_itc = 44,
AR_pfs = 64,
AR_lc = 65,
AR_ec = 66
} |
| enum | Int_Comp_Rel {
icmp_invalid = 0,
icmp_eq,
icmp_ne,
icmp_gt,
icmp_ge,
icmp_lt,
icmp_le,
icmp_gtu,
icmp_geu,
icmp_ltu,
icmp_leu
} |
| enum | Float_Comp_Rel {
fcmp_invalid = 0,
fcmp_eq,
fcmp_neq,
fcmp_lt,
fcmp_le,
fcmp_gt,
fcmp_ge,
fcmp_nlt,
fcmp_nle,
fcmp_ngt,
fcmp_nge,
fcmp_unord,
fcmp_ord
} |
| enum | Compare_Extension {
cmp_none = 0,
cmp_unc,
cmp_and,
cmp_or,
cmp_or_andcm,
cmp_last
} |
| enum | Branch_Type {
br_cond = 0,
br_ia = 1,
br_wexit = 2,
br_wtop = 3,
br_ret = 4,
br_cloop = 5,
br_cexit = 6,
br_ctop = 7,
br_call = 8
} |
| enum | Branch_Prefetch_Hint { br_few = 0,
br_many = 1
} |
| enum | Branch_Whether_Hint { br_sptk = 0,
br_spnt = 1,
br_dptk = 2,
br_dpnt = 3
} |
| enum | Branch_Dealloc_Hint { br_none = 0,
br_clr = 1
} |
| enum | Branch_Important_Hint { br_not_imp = 0,
br_imp = 1
} |
| enum | Branch_Predict_Whether_Hint { brp_sptk = 0,
brp_none = 1,
brp_dptk = 2
} |
| enum | Sxt_Size { sxt_size_1 = 0,
sxt_size_2 = 1,
sxt_size_4 = 2,
sxt_size_invalid = 3
} |
| enum | Float_Precision { float_none = 0,
float_s = 1,
float_d = 2,
float_parallel = 3
} |
| enum | Float_Status_Field { sf0 = 0,
sf1 = 1,
sf2 = 2,
sf3 = 3
} |
| enum | FReg_Convert { freg_sig = 0,
freg_exp = 1,
freg_s = 2,
freg_d = 3
} |
| enum | FFix_Convert { ffix_s = 0,
ffix_u = 1,
ffix_s_tr = 2,
ffix_u_tr = 3
} |
| enum | Float_Merge { fmerge_s = 0,
fmerge_ns = 1,
fmerge_se = 2
} |
| enum | Int_Mem_Size { int_mem_size_1 = 0,
int_mem_size_2 = 1,
int_mem_size_4 = 2,
int_mem_size_8 = 3
} |
| enum | Float_Mem_Size { float_mem_size_s = 2,
float_mem_size_d = 3,
float_mem_size_8 = 1,
float_mem_size_e = 0
} |
| enum | Ld_Flag {
mem_ld_none = 0,
mem_ld_s = 1,
mem_ld_a = 2,
mem_ld_sa = 3,
mem_ld_bias = 4,
mem_ld_acq = 5,
mem_ld_fill = 6,
mem_ld_c_clr = 8,
mem_ld_c_nc = 9,
mem_ld_c_clr_acq = 10
} |
| enum | St_Flag { mem_st_none = 0,
mem_st_rel = 1,
mem_st_spill = 2
} |
| enum | Cmpxchg_Flag { mem_cmpxchg_acq = 0,
mem_cmpxchg_rel = 1
} |
| enum | Mem_Hint { mem_none = 0,
mem_ntl = 1,
mem_nta = 3
} |
| enum | Lfetch_Hint { lfetch_none = 0,
lfetch_nt1 = 1,
lfetch_nt2 = 2,
lfetch_nta = 3
} |
| enum | Xla_Flag { l_form = 0,
h_form = 3,
hu_form = 2
} |
Variables |
| Template_Descr | tmplt_descr [] |